1. Field of the Invention
This invention relates to the fabrication of integrated circuits (IC) and, more particularly, to the fabrication of IC comprising metal oxide semiconductor field-effect transistors (MOSFET) employing shallow junction formation.
2. Description of the Prior Art
Incorporated by reference herein is U.S. patent application Ser. No. 08/792,107, filed Jan. 31, 1997 and assigned to the assignee of the present application. The present invention and the aforesaid patent application are concerned with alternative solutions to a problem which arises in the fabrication of MOSFETs (e.g., CMOS field-effect transistors), having gate length dimensions that are scaled down from 0.25 .mu.m to only 0.18 .mu.m. For the 0.18 .mu.m CMOS technology, these junctions depths are projected, by the Semiconductor Industry Association's "The National Technical Roadmap for Semiconductors" (1995), to be less than 80 nm.
The first step of each of these alternative solutions is to amorphize a selected surface layer of crystalline silicon of each MOSFET to a selected depth. However, the remaining steps of each of these alternative solutions are different from one another.
In the case of the solution disclosed in the aforesaid patent application, a selected amount of doping material is deposited as a film on the surface of the amorphized selected surface layer of the silicon and then at least a portion of the amorphized selected surface layer of the silicon is temporarily heated, using prior-art projection gas immersion laser doping (P-GILD), for a certain time to a temperature which is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon (since the melting temperature of amorphized silicon is substantially below that of crystalline silicon). P-GILD is a relatively new technique, known in the art, for doping silicon that eliminates up to 11 steps in the current process and can produce very shallow, sharply-defined regions of doping covering a wide range of doping concentrations. A revolutionary approach to impurity incorporation at precise locations in the silicon, P-GILD eliminates the need to build a mask on the wafer in order to define the regions to be doped prior to implantation. In accordance with the teaching of the aforesaid patent application, doping depth (and, hence, the depth of the junctions being formed in the selected surface layer) is determined solely by the depth of the melted amorphized selected surface layer. After the completion of the certain heating time, the melted silicon of the heated portion is permitted to cool, thereby effecting a recrystallization of the silicon of this portion of the selected surface layer. Finally, the recrystallized silicon of this portion of the selected surface layer may be annealed.
As known, amorphization implants produce supersaturation of point defects. Upon annealing, point defect injection results in nucleation of extended defects. A critical annealing temperature applied for a selected time (e.g., 1050.degree. C. for 10 sec.) by means of conventional rapid thermal processes is ordinarily required to anneal out the extended defects. However, the laser melting of the amorphized silicon by the P-GILD doping operation inherently provides a certain amount of annealing. Further, due to the small number of point defects present after the laser process, the junctions are not likely to move much as a result of this thermal cycle. Therefore, as speculated in the aforesaid patent application, no additional anneal for laser annealed junctions may be necessary. However, as further speculated in the aforesaid patent application, the exact extent of the diffusion after laser annealing needs to be determined experimentally in order to determine if any additional annealing is necessary.
The solution provided by the present invention employs prior-art ion implantation of dopants in at least a portion of the selected amorphized surface layer of the silicon and then the surface layer of the silicon is temporarily heated, using laser thermal annealing (LTA), for a certain time to a temperature which is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon (since the melting temperature of amorphized silicon is substantially below that of crystalline silicon). After the completion of the certain heating time, the melted silicon of the heated portion is permitted to cool, thereby effecting a recrystallization of the silicon of this portion of the selected surface layer.
Although the LTA process is similar in certain respects to the P-GILD process, the LTA process is materially different in other respects from the P-GILD process. In both processes, a selected area of a silicon wafer is immersed in a gas and high-power projected laser radiation is used to heat the immersed gas and those particular regions of the wafer surface that are then being illuminated by the radiation. However, the immersion gas employed in the P-GILD process is an active gas which includes vaporized dopants, while the immersion gas employed in the LTA process is a relatively inert gas, such as nitrogen. Further, in the P-GILD process, the resolution capability of the projection optics must be high enough to accurately image a group of spaced reticle patterns on a corresponding group of sharply-defined spaced regions of doping of the silicon wafer. In the LTA process, however, the resolution capability of the projection optics (which need be only sufficient to flood the entire selected area of the silicon wafer with the illuminating radiation) is significantly lower than the high resolution capability of the projection optics needed by the P-GILD process. Therefore, it is plain that projection optics suitable for use with the LTA process is simpler and less costly than projection optics suitable for use with the P-GILD process. However, for the LTA process to be manufacturable in the fabrication of MOSFETs employing shallow junction formation, the process margins must be large enough to account for laser illumination energy fluctuations. This condition can be met with the correct choice of lasers and proper spatial homogenization of the laser illumination.
Nevertheless, problems arise in the fabrication of MOSFETs employing shallow junctions when the LTA process is applied directly to the silicon wafer surface at the point in the fabrication process that follows the implantation of dopants in the amorphized silicon layer. These problems are due to the fact that the silicon wafer surface is not a uniform absorber of the incident radiation. This non-uniformity results in geometry effects over the radiation-flooded selected area that cause fluctuations and shifts in the melt threshold of the shallow-junction MOSFETs being fabricated. Such melt threshold shifts introduce too much variability for the LTA process, as known, to be viable.
The present invention addresses this melt-threshold-shift shortcoming, thereby making the LTA process manufacturable in the fabrication of a plurality of shallow-junction MOSFETs, which MOSFETs are spaced from one another by substantially transparent isolation elements.